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| 0 R Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) 5 DS030 (v1.10) November 18, 2002 0 Product Specification Introduction The family of PROMs provides an easy-to-use, cost-effective method for storing Spartan device configuration bitstreams. When the Spartan device is in Master Serial mode, it generates a configuration clock that drives the Spartan PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the Spartan device D IN pin. The Spartan device generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When a Spartan device is in Slave Serial mode, the PROM and the Spartan device must both be clocked by an incoming signal. For device programming, either the Xilinx Alliance or the Foundation series development systems compiles the Spartan device design file into a standard HEX format which is then transferred to most commercial PROM programmers. SpartanTM Spartan PROM Features * Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan, Spartan-XL, and Spartan-II FPGA devices Simple interface to the Spartan device requires only one user I/O pin Programmable reset polarity (active High or active Low) Low-power CMOS floating gate process Available in 5V and 3.3V versions Available in compact plastic 8-pin DIP, 8-pin VOIC, or 20-pin SOIC packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Guaranteed 20 year life data retention Compatible Spartan PROM XC17S05 XC17S05XL XC17S10 XC17S10XL XC17S20 XC17S20XL XC17S30 XC17S30XL XC17S40 XC17S40XL XC17S50XL XC17S100XL XC17S150XL * * * * * * * * Spartan FPGA XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL XC2S50(1) XC2S100(1) XC2S150(1) Configuration Bits 53,984 54,544 95,008 95,752 178,144 179,160 247,968 249,168 329,312 330,696 559,200 781,216 1,040,096 Notes: 1. For new Spartan-II designs, it is recommended to use the 17S00A family. (c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS030 (v1.10) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 1 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) R Pin Description Pins not listed are "no connects." Table 1: Spartan PROM Pinouts 8-pin PDIP (PD8) and VOIC/TSOP (VO8) 1 20-pin SOIC (SO20) 1 Pin Name DATA Pin Description Data output, High-Z state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin. CLK RESET/OE (OE/RESET) 2 3 3 8 CE 4 10 When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. GND is the ground connection. The VCC pins are to be connected to the positive voltage supply. GND VCC 5 7, 8 11 18, 20 Pinout Diagrams DATA(D0) NC CLK NC NC NC NC OE/RESET NC CE 1 2 3 4 5 6 7 8 9 10 SO20 Top View 20 19 18 17 16 15 14 13 12 11 VCC NC VCC NC NC NC NC NC NC GND DS030_04_110102 DATA(D0) CLK OE/RESET CE 1 2 8 VCC VCC NC GND DS030_05_110102 PD8/ 7 VO8/SO8 3 Top View 6 4 5 2 www.xilinx.com 1-800-255-7778 DS030 (v1.10) November 18, 2002 Product Specification R Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) temporary signal CCLK, which is generated during configuration. Master Serial mode provides a simple configuration interface (Figure 1). Only a serial data line and two control lines are required to configure the Spartan device. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the Spartan device is used only for configuration, it must still be held at a defined level during normal operation. The Spartan family takes care of this automatically with an on-chip default pull-up resistor. Controlling PROMs Connecting the Spartan device with the PROM: * * * The DATA output of the PROM drives the DIN input of the lead Spartan device. The Master Spartan device CCLK output drives the CLK input of the PROM. The RESET/OE input of the PROM is driven by the INIT output of the Spartan device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods--such as driving RESET/OE from LDC or system reset--assume that the PROM internal power-on-reset is always in step with the FPGAs internal power-on-reset, which may not be a safe assumption. The CE input of the PROM is driven by the DONE output of the Spartan device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Programming the FPGA With Counters Unchanged Upon Completion When multiple-configurations for a single Spartan device are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the Spartan device configuration process. The Spartan device aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the Spartan device is the Master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the Spartan device configuration will be completely wrong, with potential contentions inside the Spartan device and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. * FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the Spartan device MODE pin. In Master Serial mode, the Spartan device automatically loads the configuration program from an external memory. The Spartan PROM has been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, the Spartan device enters the Master Serial mode when the MODE pin is Low. Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the DS030 (v1.10) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 3 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) R Spartan Master Serial MODE 3.3V VCC 4.7K VCC VCC DIN CCLK DONE INIT DATA CLK CE Spartan PROM OE/RESET (Low Resets the Address Pointer) CCLK (Output) DIN DOUT (Output) DS030_01_101001 Figure 1: Master Serial Mode. The one-time-programmable Spartan PROM supports automatic loading of configuration programs. An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active. 4 www.xilinx.com 1-800-255-7778 DS030 (v1.10) November 18, 2002 Product Specification R Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. Programming the Spartan Family PROMs The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. VCC GND RESET/ OE or OE/ RESET CE CLK Address Counter TC EPROM Cell Matrix Output OE DATA DS030_02_011300 Figure 2: Simplified Block Diagram (does not show programming circuit) Important: Always tie the two VCC pins together in your application. Table 2: Truth Table for XC17S00 Control Inputs Control Inputs RESET(1) Inactive Active Inactive Active CE Low Low High High Internal Address(2) If address < TC: increment If address > TC: don't change Held reset Not changing Held reset DATA Active High-Z High-Z High-Z High-Z Outputs ICC Active Reduced Active Standby Standby Notes: 1. The XC17S00 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC + 1 = address 0. DS030 (v1.10) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 5 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) R XC17S05, XC17S10, XC17S20, XC17S30, XC17S40 Absolute Maximum Ratings(1) Symbol VCC VIN VTS TSTG TSOL Description Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions(1) Symbol VCC Description Commercial Industrial Conditions Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) Min 4.75 4.50 Max 5.25 5.50 Units V V Notes: 1. During normal read operation both VCC pins must be connected together. DC Characteristics Over Operating Condition Symbol VIH VIL VOH VOL VOH VOL ICCA ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode XC17S05, XC17S10, XC17S20, XC17S30 XC17S40 IL CIN COUT Input or output leakage current Input Capacitance (VIN = GND, f = 1.0 MHz) Output Capacitance (VIN = GND, f = 1.0 MHz) Industrial Commercial Description Min 2.0 0 3.86 3.76 -10 Max VCC 0.8 0.32 0.37 10 50 100 10 10 10 Units V V V V V V mA A A A pF pF 6 www.xilinx.com 1-800-255-7778 DS030 (v1.10) November 18, 2002 Product Specification R Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL, XC17S50XL, XC17S100XL, XC17S150XL Absolute Maximum Ratings(1) Symbol VCC VIN VTS TSTG TSOL Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) Value -0.5 to +4.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V C C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions(1) Symbol VCC Description Commercial Industrial Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) Min 3.0 3.0 Max 3.6 3.6 Units V V Notes: 1. During normal read operation both VCC pins must be connected together. DC Characteristics Over Operating Condition Symbol VIH VIL VOH VOL ICCA ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode Input or output leakage current Input Capacitance (VIN = GND, f = 1.0 MHz) Output Capacitance (VIN = GND, f = 1.0 MHz) Description Min 2.0 0 2.4 -10 Max VCC 0.8 0.4 5 50 10 10 10 Units V V V V mA A A pF pF DS030 (v1.10) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 7 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) R AC Characteristics Over Operating Condition(1) CE TSCE TSCE THCE RESET/OE TLC THC TCYC THOE CLK TOE TCE TCAC TOH TDF DATA TOH DS0306_03_011300 Symbol TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE Description RESET/OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, RESET/OE, or CLK(2) Min 0 100 50 50 25 0 25 Max 45 60 80 50 - Units ns ns ns ns ns ns ns ns ns ns ns CE or RESET/OE to Data Float Delay(2,3) Clock Periods CLK Low Time(2) CLK High Time(2) CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) RESET/OE Hold Time (guarantees counters are reset) Notes: 1. AC test load = 50 pF 2. Guaranteed by design, not tested. 3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 8 www.xilinx.com 1-800-255-7778 DS030 (v1.10) November 18, 2002 Product Specification R Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) Ordering Information XC17S20XL VO8 C Device Number XC17S05 XC17S05XL XC17S10 XC17S10XL XC17S20 XC17S20XL XC17S30 XC17S30XL XC17S40 XC17S40XL XC17S50XL XC17S100XL XC17S150XL Operating Range/Processing C = Commercial (TA = 0C to +70C) I = Industrial (TA = -40C to +85C) Package Type PD8 = VO8 = SO20 = 8-pin Plastic DIP 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package Spartan 5V Valid Ordering Combinations (XC17S00) XC17S05PD8C XC17S05VO8C XC17S05PD8I XC17S05VO8I XC17S10PD8C XC17S10VO8C XC17S10PD8I XC17S10VO8I XC17S20PD8C XC17S20VO8C XC17S20PD8I XC17S20VO8I XC17S30PD8C XC17S30VO8C XC17S30PD8I XC17S30VO8I XC17S40PD8C XC17S40SO20C XC17S40PD8I XC17S40SO20I Spartan 3.3V Valid Ordering Combinations (XC17S00XL) XC17S05XLPD8C XC17S05XLVO8C XC17S05XLPD8I XC17S05XLVO8I XC17S10XLPD8C XC17S10XLVO8C XC17S10XLPD8I XC17S10XLVO8I XC17S100XLPD8C XC17S100XLSO20C XC17S100XLPD8I XC17S100XLSO20I XC17S150XLPD8C XC17S150XLSO20C XC17S150XLPD8I XC17S150XLSO20I XC17S20XLPD8C XC17S20XLVO8C XC17S20XLPD8I XC17S20XLVO8I XC17S30XLPD8C XC17S30XLVO8C XC17S30XLPD8I XC17S30XLVO8I XC17S40XLPD8C XC17S40XLSO20C XC17S40XLPD8I XC17S40XLSO20I XC17S50XLPD8C XC17S50XLSO20C XC17S50XLPD8I XC17S50XLSO20I DS030 (v1.10) November 18, 2002 Product Specification www.xilinx.com 1-800-255-7778 9 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) R Marking Information Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows. 17S20L Device Number 17S05 17S05L 17S10 17S10L 17S20 17S20L 17S30 17S30L 17S40 17S40L 17S50L 17S100L 17S150L V C Operating Range/Processing C = Commercial (TA = 0C to +70C) I = Industrial (TA = -40C to +85C) Package Mark P V S = = = 8-pin Plastic DIP 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package Note: When marking the device number on the XL parts, an L is used in place of an XL. Revision History The following table shows the revision history for this document. Date 07/14/98 09/08/98 Revision 1.1 1.2 Cosmetic edits for pages 1, 2, and 4. Clarified the SPARTAN FPGA and PROM interface by removing references to CEO pin. Removed the ESD notation in Absolute Maximum table since it is now included in Xilinx's Reliability Monitor Report. Added additional Spartan-XL parts, changed SPROM to PROM. Changed device ordering numbers, added 4.7K resistor to OE/RESET in Figure 1. Added XC17S200XL PROM for Spartan XC2S200. Updated format. Added to features: "Guaranteed 20 year life data retention." Added a note to Table 1. Changed VPP to VCC on Figure 1. Updated Table , page 1. Updated the template. Added Pinout Diagrams, page 2. Modified document title. Revision 01/20/00 02/18/00 04/04/00 08/06/00 04/07/01 10/10/01 11/04/02 11/18/02 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 10 www.xilinx.com 1-800-255-7778 DS030 (v1.10) November 18, 2002 Product Specification |
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